The HPC Advisory Council, together with Stanford University, is holding the HPC Advisory Council Stanford Conference and Exascale Workshop 2014 at Stanford, California.  I am attending the conference, and specifically today, the conference was kicked off with the first keynote from Mark Seager, CTO for the Technical Computing Ecosystem at Intel.  In his presentation, he discussed challenges such as extreme levels of parallelism and trends that technical computing segments should be aware of.

 

The presentations are being covered by InsideHPC, so if you didn't get to make it here in person, you can watch the presentations as they are posted at InsideHPC.

 

You may also find the second keynote of the day "Programming Models for Exascale Systems" from Dhabaleswar K. Panda, Ohio State University interesting as well.  He went into challenges in designing runtime environments of MPI/PGAS (UPC and OpenSHMEM programming models.  Also covered were insights into GPU computing, Intel MIC, scalable collectives.

 

Always an exceptional event - and the discussion today which was a panel session "Road to Exascale Panel", included participation from a great audience as well as the industry thought leaders, including Mellanox's CTO Michael Kagan, Intel CTO for the Technical Computing Ecosystem Mark Seager,  DK Panda from OSU,  and Alan Poston from Xyratex.

 

Also presentations from Mellanox, Intel and Cray, as well as a session on the work and progress that Michigan Technological University is doing.