Over the last decade, specialized heterogeneous hardware designs ranging from Cell over GPGPU to Intel

 

Xeon Phi have become a viable option in High Performance Computing – mostly due to the fact that these

 

heterogeneous architectures allow for a better flops-per-watt ratio than conventional multi-core designs.

 

However, the corresponding programming models for heterogeneous architectures so far remain limited.

 

Neither offload models (like Cuda from Nvidia, OpenACC or Intel offload directives) nor the native

 

execution on the accelerator (e.g execution on Intel Xeon Phi) is able to provide a single cohesive view of

 

the underlying fragmented heterogeneous memory.

 

The upcoming new GASPI standard will able to bridge this gap in the sense that GASPI can provide

 

partitioned global address spaces (so called segments), which span across both the memory of the Host

 

and e.g. an Intel Xeon Phi.

 

Download the solution brief here :  Fraunhofer ITWM demonstrates GPI 2.0 with Mellanox Connect-IB™ and Intel® Xeon Phi™