Gigantic buffers can hold packets for a very long time and make network troubleshooting difficult. Issues related to big buffers such as this and buffer bloat have been covered in the past. The focus of this blog is ultra-deep buffer implementation, related architectural choices and performance implications. Part 1 of this two-part blog series already covered on-chip packet buffer architectures.
Chipsets with ultra-deep buffers were originally designed to address the modular switch market. These chipsets with external buffers are not relevant to storage, big data and other high performance applications inside the datacenter. Let us get more into the details.