Without considering buffer architecture nuances, it is difficult for customers to ascertain if what they see in the datasheet is what they actually get. This blog presents three important buffer related questions customers can ask themselves to gain better insight into the system level performance.
I want to cover this topic in two parts. In this first part, I will go over possible architectural choices for on-chip switch packet buffers and implications. The second part will be dedicated to off-chip “ultra-deep” packet buffer architectures.