Inside the Silicon Photonics Transceiver

Version 10

    This post provides an overview of the various functional blocks needed to build cables and transceivers using silicon photonics chips. In this post we will uncover the transceiver and learn about the various building blocks inside.

    The post is intended for IT architects and managers who wish to understand silicon photonics at a deeper level.





    The transmitter portion of the silicon photonics optical engine takes multiple high-speed electrical channels, converts them to an equivalent high-speed optical signal and couples this optical signal to one or more optical fibers, supporting distances from as close as the next  rack to as far as across the entire data center. At the receive side, the optical engine couples to optical fiber and converts the optical signals back to electrical. In data centers, optical engines are emerging as the lowest power, smallest technology choice in pluggable transceivers for connecting cluster switches and routers, and are used in Active Optical Cables (AOC) to connect server blades and switches. In addition, optical engines reduce the power and increase the density in board-to-board applications.



    However, there are many challenges in integrating optical functions on a CMOS platform designed primarily for electrical functions. Unlike traditional transceivers, this one has no “gold bricks,” the industry slang for hermetically sealed gold packages containing  the Transmitter Optical Sub-Assembly (TOSA) and Receiver Optical Sub-Assembly (ROSA).  Instead of expensive, hand assembly of optical components,  the silicon photonics optical engine is mounted directly on the PCB board, in a high-volume, low-cost, electronics-style assembly process.


    Let’s open a 100 Gb/s QSFP28 package and have a look at each of the key opto-electrical functions and the challenges of full integration in a CMOS platform.






    Removing the cover, the first thing we notice is how simple it looks:

    • We can see a microprocessor which is used to manage and control the transceiver.
    • There are two silicon photonics (SIP) chips, denoted by SIP Tx (transmitter) and SIP Rx (receiver). Those chips are very small and are hidden under the Heat Sink.
    • The Heat Sink transfers the heat from the high speed electronics chips to the shell of the package.
    • The Driver (Tx) the TIA (Rx) are the high speed electronics chips connecting the silicon photonics chips to the QSFP connector pins.

    • The Fiber Ribbon Holder ensures proper alignment of the optical fibers to the silicon photonics chips.


    Since the silicon photonics chips are small and hidden by the Heat Sink Block, here are photos of the transceiver and receiver chips themselves, starting with the transceiver chip:


    The Transceiver Silicon Photonics Chip



    In the Tx silicon chip, a single laser is coupled to a single waveguide. The light travels through the waveguide to a splitter (lower left corner) which splits the light from a single laser source into four waveguides. The four large blocks along the left side are the drive pads for the four modulators. The modulators are very small, located in the very middle of each drive pad. Each modulator operates at 25 Gb/s;  in this 100Gb/s transceiver, four 25Gb/s lanes are used.


    Lasers: Lasers provide the source of light for the optical engine, and high-speed lasers are usually expensive. However, Mellanox has developed  on-chip functions that use the light from low-cost, low-speed lasers. Although the laser is the one optical component that is not monolithically integrated on the silicon chip, recent developments in flip-chip bonding of lasers and arrays make this a high-volume, low-cost process. Silicon features eliminate the need for any lenses, isolators and beam collimators traditionally used in laser sub-assembly. Mellanox’s laser design also eliminates the need for expensive hermetic packaging. It just takes a few seconds on an automated station to align and bond a laser array to the silicon photonics chip. Mellanox has solved one of the toughest problems, which is getting a low-cost light source into the chip.


    Modulators: The lowest-cost, most efficient scheme is to directly convert the electrical lanes to optical. This means that the modulators must work at the highest electrical data rate so the conversion can happen. 100Gb/s nets are physically four 25Gb/s electrical lanes (which are treated by all of the network elements as a 100Gb/s pipe), so the modulator must be 25Gb/s or faster.

    There are other constraints:

    • The drive voltage must be CMOS compatible.
    • The modulator must exhibit great extinction ratio at 25G.
    • It must be low power.
    • It must work over a broad spectrum of light.
    • It has to be small.


    Mellanox has developed an electro-absorption (EA) modulator (also called Franz Keldysh - FK Modulators) that is 25 times smaller than a traditional Mach-Zehnder Interferometer (MZI) style modulator. The length of the FK modulator is less than 50 µm; a competing  MZI version would be measured in millimeters. This small size reduces the drive capacitance and power consumption. Additionally, the drivers can be implemented in pure CMOS – and the modulator works at speeds of 40Gb/s and higher.


    The Receiver Silicon Photonics Chip



    The key building blocks for the receiver chip are the detectors, also monolithically integrated into a silicon chip.


    Detectors: On the Rx side, the optical fibers are connected at the edge of the chip to four waveguides which transmit the optical signals to four detectors, located at the right edge of the chip. Germanium photo detectors (Ge PDs) convert the optical signal to electrical. Four power-efficient TIAs (Transimpedance Amplifiers) boost the small electrical current from the detectors to normal electrical signals.


    The above chips, packaged in a low-cost QSFP28 form factor, enable transmission of 100 Gb/s data streams for a distance of 2km or more.